I am a PhD student at Airbus
. I work in the areas of real-time scheduling on multi/many-core processors and mixed critical systems with a specific focus on aerospace-related problems such as software certification.
Although I was born in Vincennes
, I spent the first 20 years of my life in Tarbes
and the rest of the time in Paris, the UK and Toulouse
where I am doing my PhD.
Embedded Software Engineer - Ph. D. Candidate
- Designed an execution model for the Kalray MPPA256 many-core processor enabling the predictable execution of temporally isolated applications using low level management of shared resources such as the DDR-SDRAM controllers, the Network-on-Chip and the on-chip SRAM.
- Implemented a custom hypervisor in bare-metal on the MPPA256 to enforce the respect of the rules imposed by the execution model and to enable the software-based Time Division Multiplexing access to the Network-on-Chip.
- Developed a real-time scheduling tool enabling the automatic mapping of large avionics applications onto the MPPA architecture in order to make the connection between the high level models of applications and the low level implementation constraints.
Electronics Engineer - Intern
Airbus - Toulouse, France
- Duration: 6 months
- Designed a tool to enable systematic verification of the conductivity requirements of the A350's Electrical Structural Network (ESN) in degraded modes using Graph algorithms.
Research Assistant - Intern
- Duration: 15 weeks
- Developed a real-time scheduling algorithm taking into account distributed systems issues (especially data locality and task migration costs).
Ph. D. Candidate
- Title : Language and Method for Predictable Execution on Many-core Processors
- Advisors : Claire Pagetti (ONERA), Éric Noulard (ONERA), Pascal Maurère (Airbus) and Benoît Triquet (Airbus)
- Context : CIFRE (Industrial Agreement of Training through Research) Agreement Airbus / ONERA
- Doctoral school : EDMITT/ISAE
- Duration : from the 1st of March 2014 to the 28th of February 2017
Diplôme d'ingénieur (equivalent MSc)
- Major : Electronics and Control Theory
- Minor : Critical Embedded Systems
- The MSc on Critical Embedded Systems focuses on the capacity to design, produce and implement real-time advanced applications taking into account the time constraints of safety critical embedded systems. Moreover, the concepts of control theory and digital electronics are addressed.
Diplôme Universitaire et Technologie (DUT)
- Undergraduate degree comparable with an Associate degree.
- Topic: Industrial Computing and Electronics (GEII)
Temporal isolation of hard real-time applications on many-core processors
in 22nd IEEE Real-Time Embedded Technology and Applications Symposium (RTAS'16)
- Bibtex and link
- Abstract: Many-core processors offer massively parallel computation power representing a good opportunity for the design of highly integrated avionics systems. Such designs must face several challenges among which 1) temporal isolation must be ensured between applications and 2) bounds of WCET must be computed for real-time safety critical applications. In order to partially address those issues, we propose an appropriate execution model, that restricts the applications behaviours, which has been implemented on the Kalray MPPA-256. We tested the correctness of the approach through a series of benchmarks and the implementation of a case study.
Predictable composition of memory accesses on many-core processors
in Embedded Real Time Software and Systems (ERTS'16)
Embedded Computing Platforms Award
- Bibtex and link
- Abstract: The use of many-core COTS processors in safety critical embedded systems is a challenging research topic. The predictable execution of several applications on those processors is not possible without a precise analysis and mitigation of the possible sources of interference. In this paper, we identify the external DDR-SDRAM and the Network on Chip to be the main bottlenecks for both average performance and predictability in such platforms. As DDR-SDRAM memories are intrinsically stateful, the naive calculation of the Worst-Case Execution Times (WCETs) of tasks involves a significantly pessimistic upper-bounding of the memory access latencies. Moreover, the worst-case end-to-end delays of wormhole switched networks cannot be bounded without strong assumptions on the system model because of the possibility of deadlock. We provide an analysis of each potential source of interference and we give recommendations in order to build viable execution models enabling efficient composable computation of worst-case end-to-end memory access latencies compared to the naive worst-case-everywhere approach.
A deadline scheduler for jobs in distributed systems
in 27th International Conference on Advanced Information Networking and Applications Workshops (WAINA’13)
- Bibtex and link
- Abstract: This study presents a soft deadline scheduler for distributed systems that aims of exploring data locality management. In Hadoop, neither the Fair Scheduler nor the Capacity Scheduler takes care about deadlines defined by the user for a job. Our algorithm, named as Cloud Least Laxity First (CLLF), minimizes the extra-cost implied from tasks that are executed over a cloud setting by ordering each of which using its laxity and locality. By using our deadline scheduling algorithm, we demonstrate prosperous performance, as the number of available nodes needed in a cluster in order to meet all the deadlines is minimized while the total execution time of the job remains in acceptable levels. To achieve this, we compare the ability of our algorithm to meet deadlines with the Time Shared and the Space Shared scheduling algorithms. At last we implement our solution in the CloudSim simulation framework for producing the experimental analysis.